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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion flash memory data sheet tm
ds05-20850-4e fujitsu semiconductor data sheet flash memory cmos 8m (1m 8) bit mbm29f080a -55/-70/-90 n n n n general description the mbm29f080a is a 8 m-bit, 5.0 v-only flash memory organized as 1 m bytes of 8 bits each. the 1 m bytes of data is divided into 16 sectors of 64 k bytes for flexible erase capability. the 8 bit of data will appear on dq 0 to dq 7 . the mbm29f080a is offered in a 48-pin tsop(i), 40-pin tsop, and 44-pin sop packages. this device is designed to be programmed in-system with the standard system 5.0 v v cc supply. a 12.0 v v pp is not required for program or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard mbm29f080a offers access times between 55 ns and 90 ns allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29f080a is command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0 v flash or eprom devices. the mbm29f080a is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. each sector can be programmed and verified in less than 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. (continued) n n n n product line up part no. mbm29f080a ordering part no. v cc = 5.0 v 5% -55 v cc = 5.0 v 10% -70 -90 max address access time (ns) 55 70 90 max ce access time (ns) 55 70 90 max oe access time (ns) 30 30 40
mbm29f080a -55/-70/-90 2 (continued) this device also features a sector erase architecture. the sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors. a sector is typically erased and verified within 1 second (if already completely preprogrammed). the mbm29f080a is erased when shipped from the factory. the mbm29f080a device also features hardware sector group protection. this feature will disable both program and erase operations in any combination of eight sector groups of memory. a sector group consists of four adjacent sectors grouped in the following pattern: sectors 0-1, 2-3, 4-5, 6-7, 8-9, 10-11, 12-13, and 14-15. fujitsu has implemented an erase suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a non-busy sector. thus, true background erase can be achieved. the device features single 5.0 v power supply operation for both read and program functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations during power transitions. the end of program or erase is detected by data polling of dq 7 , or by the toggle bit i feature on dq 6 or ry/by output pin. once the end of a program or erase cycle has been completed, the device automatically resets to the read mode. the mbm29f080a also has a hardware reset pin. when this pin is driven low, execution of any embedded program or embedded erase operations will be terminated. the internal state machine will then be reset into the read mode. the reset pin may be tied to the system reset circuity. therefore, if a system reset occurs during the embedded program or embedded erase operation, the device will be automatically reset to a read mode. this will enable the system microprocessor to read the boot-up firmware from the flash memory. fujitsu's flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29f080a memory electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection. n features ? single 5.0 v read, write, and erase minimizes system level power requirements ? compatible with jedec-standard commands pinout and software compatible with single-power supply flash superior inadvertent write protection ? 48-pin tsop(i) (package suffix: pftn-normal bend type, pftr-reverse bend type) 40-pin tsop(i) (package suffix: ptn-normal bend type, ptr-reversed bend type) 44-pin sop (package suffix: pf) ? minimum 100,000 write/erase cycles ? high performance 55 ns maximum access time ? sector erase architecture uniform sectors of 64 k bytes each any combination of sectors can be erased. also supports full chip erase. ? embedded erase? algorithms automatically pre-programs and erases the chip or any sector ? embedded program? algorithms automatically programs and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ?low v cc write inhibit 3.2 v (continued)
mbm29f080a -55/-70/-90 3 (continued) ? hardware reset pin resets internal state machine to the read mode ? erase suspend/resume supports reading or programming data to a sector not being erased ? sector group protection hardware method that disables any combination of sector groups from write or erase operation (a sector group consists of 2 adjacent sectors of 64 k bytes each) ? temporary sector groups unprotection temporary sector unprotection via the reset pin n n n n packages 40-pin plastic tsop(1) (fpt-40p-m06) 40-pin plastic tsop(1) (fpt-40p-m07) marking side marking side 48-pin plastic tsop(1) (fpt-48p-m19) 48-pin plastic tsop(1) (fpt-48p-m20) marking side marking side 44-pin plastic sop (fpt-44p-m16)
mbm29f080a -55/-70/-90 4 n n n n pin assignments (continued) a 19 a 18 a 17 a 16 a 15 a 14 reset a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 n.c. oe dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 a 0 a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 44 43 42 41 mbm29f080a normal bend tsop(i) fpt-48p-m19 (marking side) a 13 a 12 ce v cc n.c. 17 18 19 20 36 35 34 33 40 39 38 37 v ss v ss v cc ry/by we n.c. 21 22 23 24 48 47 46 45 n.c. n.c. n.c. n.c. n.c. n.c. n.c. a 19 a 18 a 17 a 16 a 15 a 14 reset a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 n.c. oe dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 a 0 a 1 a 2 a 3 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 41 42 43 44 45 46 47 48 29 30 31 32 mbm29f080a reverse bend fpt-48p-m20 (marking side) a 13 a 12 ce v cc n.c. 8 7 6 5 37 38 39 40 33 34 35 36 v ss v ss v cc ry/by we n.c. 4 3 2 1 25 26 27 28 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c.
mbm29f080a -55/-70/-90 5 (continued) pin name function a 19 to a 0 address inputs dq 0 to dq 7 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/sector protection unlock n.c. no internal connection v ss device ground v cc device power supply (5.0 v 10%) a 19 a 18 a 17 a 16 a 15 a 14 reset a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 n.c. oe dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 12 a 15 a 16 a 18 v cc ce a 17 a 14 a 13 a 8 a 9 a 10 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss dq 3 dq 4 dq 5 dq 6 dq 7 we n.c. oe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 21 22 23 24 25 26 27 28 29 30 31 32 mbm29f080a normal bend mbm29f080a reverse bend tsop(i) fpt-40p-m06 fpt-40p-m07 marking side marking side a 13 a 12 ce v cc n.c. 17 18 19 20 36 35 34 33 40 39 38 37 v ss v ss v cc ry/by we n.c. a 11 reset n.c. a 19 20 19 18 17 37 38 39 40 v ss v cc ry/by n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 44 43 42 41 36 35 34 33 40 39 38 37 27 26 25 24 23 reset n.c. a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 n.c. n.c. sop fpt-44p-m16 v cc ce a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 n.c. n.c. n.c. n.c. we oe ry/by dq 7 dq 6 dq 5 dq 4 v cc a 0 a 1 a 2 a 3 dq 3 dq 2 dq 1 dq 0 v ss v ss (top view)
mbm29f080a -55/-70/-90 6 n n n n logic symbol n n n n block diagram 20 a 19 to a 0 we oe ce dq 7 to dq 0 8 reset ry/by v ss v cc we ce a 19 to a 0 oe erase voltage generator dq 7 to dq 0 state control command register program voltage generator low v cc detector address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb timer for reset ry/by buffer ry/by program/erase
mbm29f080a -55/-70/-90 7 n n n n flexible sector-erase architecture mbm29f080a user bus operations table legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. refer to mbm29f080a command definitions table in n flexible sector-erase architecture. *2 : refer to the section on sector group protection. *3 : we can be v il if oe is v il , oe at v ih initiates the write operations. mbm29f080a sector protection verify autoselect codes table * : outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. operation ce oe we a 0 a 1 a 6 a 9 dq 0 to dq 7 reset auto-select manufacturer code * 1 llhlllv id code h auto-select device code * 1 llhhllv id code h read * 3 llha 0 a 1 a 6 a 9 d out h standby hxxxxxx high-z h output disable lhhxxxx high-z h write (program/erase) l h l a 0 a 1 a 6 a 9 d in h enable sector group protection * 2 lv id xxxv id xh verify sector group protection * 2 llhlhlv id code h temporary sector group unprotection x x x x x x x x v id reset (hardware) x x x x x x x high-z l type a 17 to a 19 a 6 a 1 a 0 code (hex) dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code xxxv il v il v il 04h00000100 device code x x x v il v il v ih d5h10101101 sector group protection sector group addresses v il v ih v il 01h* 0 0 0 0 0 0 0 1
mbm29f080a -55/-70/-90 8 sector address table sector group addresses table a 19 a 18 a 17 a 16 address range sa0 0 0 0 0 000000h to 00ffffh sa1 0 0 0 1 010000h to 01ffffh sa2 0 0 1 0 020000h to 02ffffh sa3 0 0 1 1 030000h to 03ffffh sa4 0 1 0 0 040000h to 04ffffh sa5 0 1 0 1 050000h to 05ffffh sa6 0 1 1 0 060000h to 06ffffh sa7 0 1 1 1 070000h to 07ffffh sa8 1 0 0 0 080000h to 08ffffh sa9 1 0 0 1 090000h to 09ffffh sa10 1 0 1 0 0a0000h to 0affffh sa11 1 0 1 1 0b0000h to 0bffffh sa12 1 1 0 0 0c0000h to 0cffffh sa13 1 1 0 1 0d0000h to 0dffffh sa14 1 1 1 0 0e0000h to 0effffh sa15 1 1 1 1 0f0000h to 0fffffh a 19 a 18 a 17 sectors sga0 0 0 0 sa0 to sa1 sga1 0 0 1 sa2 to sa3 sga2 0 1 0 sa4 to sa5 sga3 0 1 1 sa6 to sa7 sga4 1 0 0 sa8 to sa9 sga5 1 0 1 sa10 to sa11 sga6 1 1 0 sa12 to sa13 sga7 1 1 1 sa14 to sa15
mbm29f080a -55/-70/-90 9 mbm29f080a command definitions table notes : address bits a 11 to a 19 = x = h or l for all address commands except or program address (pa) and sector address (sa). bus operations are defined in mbm29f080a user bus operations table in n flexible sector- erase architecture. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a 19 , a 18 , a 17 , and a 16 will uniquely select any sector. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we . read and byte program functions to non-erasing sectors are allowed in the erase suspend mode. the system should generate the following address pattens: 555h or 2aah to addresses a 0 to a 10 . the command combinations not described in mbm29f080a command definitions table in n flexible sector-erase architecture are illegal. *1: either of the two reset commands will reset the device. *2: the fourth bus cycle is only for read. command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset* 1 1 xxxh f0h reset/read* 1 3 555h aah 2aah 55h 555h f0h ra* 2 rd* 2 manufacture code 3 555h aah 2aah 55h 555h 90h 00h* 2 04h* 2 device code 3 555h aah 2aah 55h 555h 90h 01h* 2 05h* 2 byte program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend erase can be suspended during sector erase with addr (h or l), data (b0h) sector erase resume erase can be resumed after suspend with addr (h or l), data (30h)
mbm29f080a -55/-70/-90 10 ? thirty two 64 k byte sectors ? 8 sector groups each of which consists of 2 adjacent sectors in the following pattern; sectors 0-1, 2-3, 4-5, 6-7, 8-9, 10-11, 12-13, and 14-15 ? individual-sector or multiple-sector erase capability ? sector group protection is user-definable 0fffffh 0effffh 0dffffh 0cffffh 0bffffh 0affffh 09ffffh 08ffffh 07ffffh 06ffffh 05ffffh 04ffffh 03ffffh 02ffffh 01ffffh 00ffffh 000000h sa15 sa14 sector group 7 sector group 0 64 k byte 64 k byte 16 sectors total 64 k byte 64 k byte sa1 sa0
mbm29f080a -55/-70/-90 11 n n n n functional description read mode the mbm29f080a has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc -t oe time). standby mode there are two ways to implement the standby mode on the mbm29f080a device, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a. a ttl standby mode is achieved with ce and reset pins held at v ih . under this condition the current is reduced to approximately 1 ma. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = v ih . the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current consumed is less than 5 m a. a ttl standby mode is achieved with reset pin held at v il (ce = h or l). under this condition the current required is reduced to approximately 1 ma. once the reset pin is taken high, the device requires 500 ns of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all addresses are don't cares except a 0 , a 1 , and a 6 . (see mbm29f080a sector protection verify autoselect codes ta b l e i n n flexible sector-erase architecture.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29f080a is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in mbm29f080a command definitions table in n flexible sector-erase ar- chitecture. (refer to autoselect command section.) byte 0 (a 0 = v il ) represents the manufacturer's code (fujitsu = 04h) and byte 1 (a 0 = v ih ) represents the device identifier code for mbm29f080a = d5h. these two bytes are given in the mbm29f080a sector protection verify autoselect codes table in n flexible sector-erase architecture. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see mbm29f080a sector protection verify autoselect codes table in n flexible sector-erase architecture.)
mbm29f080a -55/-70/-90 12 the autoselect mode also facilitates the determination of sector group protection in the system. by performing a read operation at the address location xx02h with the higher order address bits a 17 , a 18 and a 19 set to the desired sector group address, the device will return 01h for a protected sector group and 00h for a non-protected sector group. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector group protection the mbm29f080a features hardware sector group protection. this feature will disable both program and erase operations in any combination of eight sector groups of memory. each sector group consists of four adjacent sectors grouped in the following pattern: sectors 0-1, 2-3, 4-5, 6-7, 8-9, 10-11, 12-13, and 14-15 (see sector group address table in n flexible sector-erase architecture). the sector group protection feature is enabled using programming equipment at the user's site. the device is shipped with all sector groups unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il . the sector addresses (a 19 , a 18 , and a 17 ) should be set to the sector to be protected. sector address table and sector group address table in n flexible sector-erase architecture define the sector address for each of the thirty two (16) individual sectors, and the sector group address for each of the eight (8) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see temporary sector group unprotection timing diagram in n timing diagram and temporary sector group unprotection algorithm in n flow chart for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 19 , a 18 , and a 17 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 19 , a 18 , and a 17 ) are the desired sector group address will produce a logical 1 at dq 0 for a protected sector group. see mbm29f080a sector protection verify autoselect codes table in n flexible sector-erase architec- ture for autoselect codes. temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the mbm29f080a device in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once the 12 v is taken away from the reset pin, all the previously protected sector
mbm29f080a -55/-70/-90 13 groups will be protected again. refer to temporary sector group unprotection timing diagram in n timing diagram and temporary sector group unprotection algorithm in n flow chart. command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. mbm29f080a command definitions table in n flexible sector-erase architecture defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover, both read/reset commands are functionally equivalent, resetting the device to the read mode. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desirable system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h returns the device code d5h. (see mbm29f080a sector protection verify autoselect codes table in n flexible sector-erase architecture). all manufacturer and device codes will exhibit odd parity with the dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address xx02h. scanning the sector group addresses (a 17 , a 18 , a 19 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector group. to terminate the operation, it is necessary to write the read/reset command sequence into the register and also to write the autoselect command during the operation, execute it after writing read/reset command sequence. byte programming the device is programmed on a byte-by-byte basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin.
mbm29f080a -55/-70/-90 14 this automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. (see hardware sequence flags table in n flexible sector-erase architecture.) therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if a hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still 0. only erase operations can convert 0s to 1s. embedded program tm algorithm in n flow chart illustrates the embedded programming tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section) at which time the device returns to read the mode. embedded erase tm algorithm in n flow chart illustrates the embedded erase? algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . after time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on mbm29f080a command definitions table in n flexible sector-erase architecture. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 m s otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 50 m s time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. resetting the device once execution has begun will corrupt the data in that sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for dq 3 , sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 15).
mbm29f080a -55/-70/-90 15 sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 50 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. embedded erase tm algorithm in n flow chart illustrates the embedded erase? algorithm using typical command strings and bus operations. erase suspend the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during a sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. any other command written during the erase suspend mode will be ignored except the erase resume command. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 15 m s to suspend the erase operation. when the device has entered the erase-suspended mode, the ry/by output pin and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for byte program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular byte program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase- suspended sector while the device is in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase-suspended program operation is detected by the ry/by output pin, data polling of dq 7 , or by the toggle bit i (dq 6 ) which is the same as the regular byte program operation. note that dq 7 must be read from the byte program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing.
mbm29f080a -55/-70/-90 16 write operation status *1 : performing successive read operations from the erase-suspended sector will cause dq 2 to toggle. *2 : performing successive read operations from any address will cause dq 6 to toggle. *3 : reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. dq 7 data polling the mbm29f080a device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase? algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in data polling algorithm in n flow chart. data polling will also flag the entry into erase suspend. dq 7 will switch 0 to 1 at the start of the erase suspend mode. please note that the address of an erasing sector must be applied in order to observe dq 7 in the erase suspend mode. during program in erase suspend, data polling will perform the same as in regular program execution outside of the suspend mode. for chip erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. data polling must be performed at sector address within any of the sectors being erased and not a sector that is within a protected sector group. otherwise, the status may not be valid. just prior to the completion of embedded algorithm operation dq 7 may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time and then that byte's valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operations and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle erase sus- pended mode erase suspend read (erase suspended sector) 1100toggle* 1 erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle* 2 001* 3 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29f080a -55/-70/-90 17 the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, erase suspend, erase-suspend-program mode, or sector erase time-out. (see hardware sequence flags table in n flexible sector-erase architecture.) see ac waveforms for data polling during embedded algorithm operations in n timing diagram for the data polling timing specifications and diagrams. dq 6 toggle bit i the mbm29f080a also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device at any address will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, and sector erase the toggle bit i is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the toggle bit i is valid after the last rising edge of the sector erase we pulse. the toggle bit i is active during the sector erase time out. in programming, if the sector being written to is protected, the toggle bit i will toggle for about 2 m s and then stop toggling without the data having changed. in erase, the device will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit i for about 100 m s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause dq 6 to toggle. see ac waveforms for toggle bit i during embedded algorithm operations in n timing diagram for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling dq 7 , dq 6 is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in mbm29f080a user bus operations table in n flexible sector-erase architecture. the dq 5 failure condition may also appear if a user tries to program a 1 to a location that is previously programmed to 0. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit i are valid after the initial sector erase command sequence.
mbm29f080a -55/-70/-90 18 if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands (other than erase suspend) to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. refer to hardware sequence flags table in n flexible sector-erase architecture. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase? algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase? algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. *1 : these status flags apply when outputs are read from a sector that has been erase-suspended. *2 : these status flags apply when outputs are read from the byte address of the non-erase suspended sector. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine the erase-suspend-read mode (dq 2 toggles while dq 6 does not). see also hardware sequence flags table in n flexible sector-erase architecture and dq 2 vs. dq 6 in n timing diagram. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from the erasing sector. ry/by ready/busy the mbm29f080a provides a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the device will not accept any additional program or erase commands with the exception of the erase suspend command. if the mbm29f080a is placed in an erase suspend mode, the ry/by output will be high, by means of connecting with a pull-up resistor to v cc . mode dq 7 dq 6 dq 2 program dq 7 toggles 1 erase 0 toggles toggles erase suspend read * 1 (erase-suspended sector) 1 1 toggles erase suspend program dq 7 * 2 toggles 1 * 2
mbm29f080a -55/-70/-90 19 during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during reset pulse. refer to ry/by timing diagram during program/erase operations in n timing diagram for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, several ry/by pins can be tied together in parallel with a pull-up resistor to v cc . reset hardware reset the mbm29f080a device may be reset by driving the reset pin to v il . the reset pin must be kept low (v il ) for at least 500 ns. any operation in progress will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. if a hardware reset occurs during a program operation, the data at that particular location will be indeterminate. when the reset pin is low and the internal reset is complete, the device goes to standby mode and cannot be accessed. also, note that all the data output pins are tri-stated for the duration of the reset pulse. once the reset pin is taken high, the device requires t rh of wake up time until outputs are valid for read access. the reset pin may be tied to the system reset input. therefore, if a system reset occurs during the embedded program or erase algorithm, the device will be automatically reset to read mode and this will enable the systems microprocessor to read the boot-up firmware from the flash memory. data protection the mbm29f080a is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completions of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 3.2 v (typically 3.7 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 3.2 v. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
mbm29f080a -55/-70/-90 20 n n n n absolute maximum ratings *1 : voltage is defined on the basis of v ss = gnd = 0 v. *2 : minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, input or i/o pins may underhoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. *3 : minimum dc input voltage on a 9 , oe , and reset pins are C0.5 v. during voltage transitions, a 9 , oe , and reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and power supply (v in C v cc ) does not exceed + 9.0 v. maximum dc input voltage on a 9 , oe , and reset are +13.0 v which may overshoot to + 14.0 v for periods up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions * : voltage is defined on the basis of v ss = gnd = 0 v. note : operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 40 + 85 c voltage with respect to ground all pins except a 9 , oe , and reset * 1, * 2 v in , v out - 2.0 + 7.0 v power supply voltage * 1, * 3 v cc - 2.0 + 7.0 v a 9 , oe , and reset * 2 v in - 2.0 + 13.5 v parameter symbol value unit min max ambient temperature mbm29f080a-55 t a - 20 + 70 c mbm29f080a-70/-90 - 40 + 85 c v cc supply voltages * mbm29f080a-55 v cc + 4.75 + 5.25 v mbm29f080a-70/-90 + 4.50 + 5.50 v
mbm29f080a -55/-70/-90 21 n n n n maximum overshoot / maximum undershoot 1. maximum undershoot waveform 2. maximum overshoot waveform 1 3. maximum overshoot waveform 2 +0.8 v C0.5 v 20 ns C2.0 v 20 ns 20 ns +2.0 v v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns v cc +0.5 v +13.0 v 20 ns +14.0 v 20 ns 20 ns note : this waveform is applied for a 9 , oe and reset .
mbm29f080a -55/-70/-90 22 n n n n dc characteristics *1 : the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is 2 ma/mhz, with oe at v ih . *2 : i cc active while embedded algorithm (program or erase) is in progress. *3 : applicable to sector protection function. *4 : (v id C v cc ) do not exceed 9 v. parameter symbol test conditions min max unit input leakage current i li v in = v ss to v cc , v cc = v cc max 1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max 1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max a 9 , oe , reset = 12.5 v 50 m a v cc active current * 1 i cc1 ce = v il , oe = v ih 40ma v cc active current * 2 i cc2 ce = v il , oe = v ih 45ma v cc current (standby) i cc3 v cc = v cc max, ce = v ih , reset = v ih 1ma v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v 5 m a v cc current (standby, reset) i cc4 v cc = v cc max, reset = v il 1ma v cc = v cc max, reset = v ss 0.3 v 5 m a input low level v il C0.50.8v input high level v ih 2.0v cc +0.5 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 3, * 4 v id 11.512.5v output low voltage level v ol i ol = 12.0 ma, v cc = v cc min 0.45 v output high voltage level v oh1 i oh = C2.5 ma, v cc = v cc min 2.4 v v oh2 i oh = C100 m av cc C0.4 v low v cc lock-out voltage v lko 3.24.2v
mbm29f080a -55/-70/-90 23 n n n n ac characteristics ? read only operations characteristics *1 : test conditions: output load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v or 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbol test setup -55 * 1 -70 * 2 -90 * 2 unit jedec standard min max min max min max read cycle time t avav t rc 55 70 90 ns address to output delay t avqv t acc ce = v il oe = v il 5570 90 ns chip enable to output delay t elqv t ce oe = v il 5570 90 ns output enable to output delay t glqv t oe 30 30 40 ns chip enable to output high-z t ehqz t df 20 20 20 ns output enable to output high-z t ghqz t df 20 20 20 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh 000ns reset pin low to read mode t ready 20 20 20 m s test conditions notes : mbm29f080a-55: c l = 30 pf including jig capacitance mbm29f080a-70/-90: c l = 100 pf including jig capacitance c l 5.0 v diode=1n3064 or equivalent 2.7 k w device under test diode=1n3064 or equivalent 6.2 k w *2 : test conditions: output load: 1 ttl gate and 100 pf input rise and fall times: 5 ns input pulse levels: 0.45 v or 2.4 v timing measurement reference level input: 0.8 v and 2.0 v output: 0.8 v and 2.0 v
mbm29f080a -55/-70/-90 24 ? write/erase/program operations (continued) description symbol mbm29f080a unit jedec standard -55 -70 -90 min typ max min typ max min typ max write cycle time t avav t wc 55 70 90 ns address setup time t avwl t as 00 0ns address hold time t wlax t ah 40 45 45 ns data setup time t dvwh t ds 25 30 45 ns data hold time t whdx t dh 00 0ns output enable setup time t oes 00 0ns output enable hold time read t oeh 00 0ns toggle bit i and data polling 10 10 10 ns read recover time before write t ghwl t ghwl 00 0ns read recover time before write t ghel t ghel 00 0ns ce setup time t elwl t cs 00 0ns we setup time t wlel t ws 00 0ns ce hold time t wheh t ch 00 0ns we hold time t ehwh t wh 00 0ns write pulse width t wlwh t wp 30 35 45 ns write pulse width t eleh t cp 30 35 45 ns write pulse width high t whwl t wph 20 20 20 ns write pulse width high t ehel t cph 20 20 20 ns byte programming operation t whwh1 t whwh1 888 m s sector erase operation * 1 t whwh2 t whwh2 111 s 8 8 8 s v cc setup time t vcs 50 50 50 m s rise time to v id t vidr 500 500 500 ns voltage transition time * 2 t vlht 44 4 m s write pulse width * 2 t wpp 100 100 100 m s oe setup time to we active * 2 t oesp 44 4 m s ce setup time to we active * 2 t csp 44 4 m s recover time from ry/by t rb 00 0ns
mbm29f080a -55/-70/-90 25 (continued) *1 : this does not include the preprogramming time. *2 : this timing is for sector protection operation. n n n n erase and programming performance n tsop(1) pin capacitance note : test conditions t a = + 25c, f = 1.0 mhz n sop pin capacitance notes : sampled, not 100% tested. test conditions t a = + 25c, f = 1.0 mhz description symbol mbm29f080a unit jedec standard -55 -70 -90 min typ max min typ max min typ max reset pulse width t rp 500 500 500 ns reset hold time before read t rh 50 50 50 ns program/erase valid to ry/by delay t busy 55 70 90 ns delay time from embedded output enable t eoe 30 30 40 ns parameter limits unit comments min typ max sector erase time 1 8 s excludes 00h programming prior to erasure byte programming time 8 150 m s excludes system-level overhead chip programming time 8.4 20 s excludes system-level overhead erase/program cycle 100,000 cycle parameter symbol test setup typ max unit input capacitance c in v in = 0 8 10 pf output capacitance c out v out = 0 8 10 pf control pin capacitance c in2 v in = 0 9 10 pf parameter symbol test setup typ max unit input capacitance c in v in = 0 8 10.5 pf output capacitance c out v out = 0 8 10 pf control pin capacitance c in2 v in = 0 9.5 11 pf
mbm29f080a -55/-70/-90 26 n n n n timing diagram ? key to switching waveforms (1) ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h h or l any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state we oe ce t acc t df t ce t oe dq 7 to dq 0 t rc address address stable high-z output valid high-z t oeh t oh
mbm29f080a -55/-70/-90 27 (2) ac waveforms for read operations (3) ac waveforms for alternate we controlled program operations reset t acc t oh dq 7 to dq 0 t rc address address stable high-z output valid t rh t wp t df t ds t whwh1 t wc t ah 5.0 v ce oe t rc address data t as t oe t wph t cs t dh dq 7 pd a0h d out t ce we 555h pa pa t oh data polling 3rd bus cycle t ghwl t ch d out notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles of four bus cycle sequence.
mbm29f080a -55/-70/-90 28 (4) ac waveforms for alternate ce controlled program operations t cp t ds t whwh1 t wc t ah 5.0 v we oe address data t as t cph t ws t dh dq 7 pd a0h d out ce 555h pa pa data polling 3rd bus cycle t ghel t wh notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles of four bus cycle sequence.
mbm29f080a -55/-70/-90 29 (5) ac waveforms chip/sector erase operations (6) ac waveforms for data polling during embedded algorithm operations v cc ce oe address data t wp we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t vcs t wc 55h 55h 80h aah aah 10h/ 30h t ghwl * : sa is the sector address for sector erase. addresses = 555h for chip erase. t oeh t oe t whwh1 or 2 ce oe we t df t ch t ce high-z dq 7 = valid data dq 0 to dq 6 = output flug dq 0 to dq 7 dq 7 * valid data high-z t eoe dq 7 data data dq 6 to dq 0 * : dq 7 = valid data (the device has completed the embedded operation.)
mbm29f080a -55/-70/-90 30 (7) ac waveforms for toggle bit i during embedded algorithm operations (8) ry/by timing diagram during program/erase operations (9) reset , ry/by timing diagram t oeh ce we oe dq 6 = toggle * t oes t oe dq 6 = stop toggling dq 0 to dq 7 valid dq 6 = toggle dq 6 data * : dq 6 stops toggling (the device has completed the embedded operation.) ce we ry/by rising edge of the last we signal entire programming or erase operations t busy reset t ready t rp t rb we ry/by
mbm29f080a -55/-70/-90 31 (10) ac waveforms for sector group protection timing diagram t vlht sgax sgay a 0 a 6 a 9 v id 5 v t vlht oe v id 5 v t vlht t vlht we ce t oe 01h data v cc a 1 address t wpp t oesp t csp t vcs sgax = sector group address for initial sector sgay = sector group address for next sector
mbm29f080a -55/-70/-90 32 (11) temporary sector group unprotection timing diagram (12) dq 2 vs. dq 6 reset v id 5 v we ce ry/by t vlht t vlht t vlht v cc t vcs t vidr program or erase command sequence unprotection period dq 2 * dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce * : dq 2 is read from the erase-suspended sector.
mbm29f080a -55/-70/-90 33 n n n n flow chart (1) embedded program tm algorithm no yes start program command sequence (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address last address ? programming completed program address/program data embedded algorithms
mbm29f080a -55/-70/-90 34 (2) embedded erase? algorithm start 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequence (see below) data polling or toggle bit i successfully completed erasure completed chip erase command sequence (address/command): individual sector/multiple sector erase command sequence (address/command): sector address/30h sector address/30h sector address/30h note : to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted.
mbm29f080a -55/-70/-90 35 (3) data polling algorithm fail dq 7 = data? no no dq 7 = data? dq 5 = 1? pass yes yes no start read byte (dq 0 to dq 7 ) addr. = va read byte (dq 0 to dq 7 ) addr. = va yes note : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector group addresses within the sector not being protected during sector erase or multiple sector erases operation.
mbm29f080a -55/-70/-90 36 (4) toggle bit i algorithm fail dq 6 = toggle ? yes no dq 6 = toggle dq 5 = 1 pass yes no yes start read ? (dq 7 to dq 0 ) addr. = h or l no read (dq 7 to dq 0 ) addr. = h or l ? read (dq 7 to dq 0 ) addr. = h or l read (dq 7 to dq 0 ) addr. = h or l *1 *1, *2 *1 : read toggle bit twice to determine whether it is toggling. *2 : dq 6 is rechecked even if dq 5 = 1 because dq 6 may stop toggling at the same time as dq 5 changing to 1. *1, *2
mbm29f080a -55/-70/-90 37 (5) sector group protection algorithm setup sector group addr. activate we pulse we = v ih, ce = oe = v il, (a 9 should remain v id ) yes yes no no plscnt = 1 time out 100 m s read from sector group increment plscnt no yes protect another sector start sector protection data = 01h? plscnt = 25? device failed remove v id from a 9 completed remove v id from a 9 write reset command addr. (a 19 , a 18 , a 17 ) a 1 = 1, a 0 = a 6 = 0 oe = v id , a 9 = v id , ce = v il , reset = v ih ( a 19 , a 18 , a 17 ) write reset command group?
mbm29f080a -55/-70/-90 38 (6) temporary sector group unprotection algorithm reset = v id * 1 perform erase or program operations reset = v ih start temporary sector group unprotection completed * 2 *1 : all protected sector groups unprotected. *2 : all previously protected sector groups are protected once again.
mbm29f080a -55/-70/-90 39 n nn n ordering information part no. package access time remarks MBM29F080A-55PTN mbm29f080a-70ptn mbm29f080a-90ptn 40-pin plastic tsop(1) (fpt-40p-m06) (normal bend) 55 70 90 mbm29f080a-55ptr mbm29f080a-70ptr mbm29f080a-90ptr 40-pin plastic tsop(1) (fpt-40p-m07) (reverse bend) 55 70 90 mbm29f080a-55pftn mbm29f080a-70pftn mbm29f080a-90pftn 48-pin plastic tsop(1) (fpt-48p-m19) (normal bend) 55 70 90 mbm29f080a-55pftr mbm29f080a-70pftr mbm29f080a-90pftr 48-pin plastic tsop(1) (fpt-48p-m20) (reverse bend) 55 70 90 mbm29f080a-55pf mbm29f080a-70pf mbm29f080a-90pf 44-pin plastic sop (fpt-44p-m16) 55 70 90 mbm29f080a -55 pftn device number/description mbm29f080a 8 mega-bit (1 m 8-bit) cmos flash memory 5.0 v-only read, write, and erase 64 k byte (16 sectors) pa c k a g e t y p e pftn = 48-pin thin small outline package (tsop(1) standard pinout ) pftr = 48-pin thin small outline package (tsop(1) reverse pinout) ptn = 40-pin thin small outline package (tsop(1) standard pinout ) ptr = 40-pin thin small outline package (tsop(1) reverse pinout) pf = 44-pin small outline package (sop standard pinout ) speed option see product selector guide
mbm29f080a -55/-70/-90 40 n n n n package dimensions (continued) 40-pin plastic tsop (1) (fpt-40p-m06) note 1) * : resin protrusion. (each side : + 0.15 (.006) max) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. 40-pin plastic tsop (1) (fpt-40p-m07) note 1) * : resin protrusion. (each side : + 0.15 (.006) max) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. .007 C .003 +.001 C 0.08 +0.03 0.17 "a" 0.10(.004) (mounting height) 1.10 +0.10 C 0.05 +.004 C .002 .043 (stand off) 0.10 0.05(.004 .002) (.394 .008) *10.00 0.20 0.10(.004) m (.009 .002) 0.22 0.05 (.724 .008) *18.40 0.20 (.787 .008) 20.00 0.20 lead no. index 21 20 40 1 2003 fujitsu limited f40007s-c-3-4 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part 0.50(.020) C .003 +.001 .007 C 0.08 +0.03 0.17 "a" 0.10(.004) (mounting height) 1.10 +0.10 C 0.05 +.004 C .002 .043 (stand off) 0.10 0.05(.004 .002) 0.10(.004) m (.009 .002) 0.22 0.05 (.394 .008) *10.00 0.20 (.724 .008) *18.40 0.20 (.787 .008) 20.00 0.20 lead no. index 21 20 40 1 2003 fujitsu limited f40008s-c-3-4 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part 0.50(.020)
mbm29f080a -55/-70/-90 41 (continued) 48-pin plastic tsop (1) (fpt-48p-m19) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. 48-pin plastic tsop (1) (fpt-48p-m20) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. C .003 +.001 C 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48029s-c-6-7 c 0~8 ? 0.25(.010) 0.50(.020) 0.60 0.15 (.024 .006) details of "a" part * * C .003 +.001 .007 C 0.08 +0.03 0.17 "a" (stand off height) (.004 .002) 0.10 0.05 0.10(.004) (mounting height) 12.00 0.20(.472 .008) lead no. 48 25 24 1 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48030s-c-6-7 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part * * 0.50(.020)
mbm29f080a -55/-70/-90 42 (continued) 44-pin plastic sop (fpt-44p-m16) note 1) *1 : these dimensions include resin protrusion. note 2) *2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2002 fujitsu limited f44023s-c-6-6 m 0.13(.005) 1.27(.050) 13.000.10 16.000.20 (.512.004) (.630.008) 1 1.120 C.008 +.010 C0.20 +0.25 28.45 0.10(.004) 22 23 44 C0.07 +0.08 0.42 .017 +.0031 C.0028 index 0~8 ? 0.25(.010) (mounting height) details of "a" part 2.350.15 (.093.006) C0.15 +0.10 0.20 .008 +.004 C.006 (stand off) 0.800.20 (.031.008) 0.880.15 (.035.006) C0.04 +0.03 0.17 .007 +.001 C.002 "a" * 1 * 2
mbm29f080a -55/-70/-90 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0305 ? fujitsu limited printed in japan

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